IDT82V3202NLG【PDF 25/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Pin Description

September 11, 2009

OUT2

CMOS

OUT2: Output Clock 2

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52

MHz clock is output on this pin.

I2C Programming Interface

INT_REQ

CMOS

INT_REQ: Interrupt Request

This pin is used as an interrupt request. The output characteristics are determined by the

HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).

AD0

AD1

AD2

ICMOS

AD[2:0]: Address Input 2 to 0

The address is input on these pins.

SCL

CMOS

SCL: Serial Clock Line

The serial clock is input on this pin. The clock is 400 kbit/s in Fast-mode and 3.4 Mbit/s in

High-speed mode.

SDA

I/O

CMOS

SDA: Serial Data Input/Output

This pin is used as the input/output for the serial data.

JTAG (per IEEE 1149.1)

TRST

pull-

down

CMOS

TRST: JTAG Test Reset (Active Low)

A low signal on this pin resets the JTAG test port.

This pin should be connected to ground when JTAG is not used.

TMS

pull-up

CMOS

TMS: JTAG Test Mode Select

The signal on this pin controls the JTAG test performance and is sampled on the rising edge

of TCK.

TCK

pull-

down

CMOS

TCK: JTAG Test Clock

The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge

of TCK and TDO is updated on the falling edge of TCK.

If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely

retain their state.

TDI

pull-up

CMOS

TDI: JTAG Test Data Input

The test data is input on this pin. It is clocked into the device on the rising edge of TCK.

TDO

CMOS

TDO: JTAG Test Data Output

The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.

TDO pin outputs a high impedance signal except during the process of data scanning.

This pin can indicate the interrupt of T0 selected input clock fail, as determined by the

LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details.

Power & Ground

VDDD1

VDDD2

VDDD3

VDDD4

VDDD5

VDDD6

38, 40, 41

36, 38, 39

Power

VDDDn: 3.3 V Digital Power Supply

Each VDDDn should be paralleled with ground through a 0.1 F capacitor.

Table 1: Pin Description (Continued)

Name

Pin No.

(NL68)

Pin No.

(TQFP 64)

I/O

Type

Description 1

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